Simulate the Dreams, Synthesize the expectations, Filter the thoughts, Place & Route the fundas, Integrate the Universe, To Synchronize the Rhythm of life....
 
Chips
Chip Design  
  Home
  Asic Design Flow
  Digital
  Timing Issues
  Verilog
  => Introduction
  => Getting Started
  => FAQ
  VHDL
  Simulation & Synthesis
  FPGA
  System Verilog
  PERL
  Contact
FAQ

1.      What is verilog?

2.      When Verilog came into existence?

3.      Explain the differences between ? : and if - else

4.      always @(posedge clk)

                a=b;

          always@ (posedge clk)

                b=c;

           For b = 3 and c = 5, after the first @ (posedge clk) what is the value of a?

5.      Consider the following code:

                `define FALSE 0

                `define TRUE 1   

                    initial   

                    begin   

                        a = `FALSE;

                        a <= `TRUE;

                        if (a == `TRUE)   

                            $display ("True");   

                        else   

                            $display ("False");

                    end

          What will print out? True or False?

6.      What is the advantage of using Gray code instead of Binary code while designing FIFO. 

7.      Write the Verilog Code for the Binary to Gray and Gray to Binary.

8.            Explain the differences between blocking and non blocking statements

9.            Explain the differences between tasks and functions

10.        When and Where files are used?

11.        What are PLI's"

12.        What is a random function?

13.        Explain the differences between initial and always statements?

14.        Explain the differences between $monitor, $display and $stobe

15.        What are different ways of coding fsm's

 

 
 
   
Today, there have been 21 visitors (28 hits) on this page!
This website was created for free with Own-Free-Website.com. Would you also like to have your own website?
Sign up for free