System Verilog adds several data types to the existing Verilog 2001 data types. 

Integer Data Types

• shortint: 2-state, 16 bit signed integer                //System  Verilog
• int:      2-state, 32 bit signed integer                 //System  Verilog
• longint:  2-state, 64 bit signed integer                //System  Verilog
• byte:    2-state, 8 bit signed integer or ascii character    //System  Verilog
• bit:      2-state, user-defined vector size           //System  Verilog
• logic:    4-state, user-defined vector size           //System  Verilog
• reg:     4-state, user-defined vector size          //Verilog 2001
• integer: 4-state, 32 bit signed integer               //Verilog 2001
• time:    4-state, 64-bit unsigned integer           //Verilog 2001

2-state (two-value) and 4-state (four-value) data types

Types that can have unknown and high-impedance values are called 4-state types. These are logic, reg, integer and time. The other types do not have unknown values and are called 2-state types, for example bit and int.

2-state data types can simulate faster, take less memory, and are preferred in some design styles.

Signed and unsigned data types

Integer types use integer arithmetic and can be signed or unsigned. This affects the meaning of certain operators such as ‘<’, etc.

int unsigned a;

int signed b;

Real Data Types

The real data type is from Verilog-2001, and is the same as a C double. The shortreal data type is a SystemVerilog data type, and is the same as a C float.

Void Data Type

The void data type represents non-existent data. This type can be specified as the return type of functions, indicating no return value.

String Data Type

Verilog supports string literals, but only at the lexical level. In Verilog, string literals behave like packed arrays of a width that is a multiple of 8 bits. SystemVerilog includes a string data type, which is a variable size, dynamically allocated array of bytes. SystemVerilog also includes a number of special methods to work with strings.

Variables of type string can be indexed from 0 to N-1 (the last element of the array), and they can take on the special value “”, which is the empty string. Reading an element of a string yields a byte.

The syntax to declare a string is:

string variable_name [= initial_value];

e.g

string myName = "System Verilog";

If an initial value is not specified in the declaration, the variable is initialized to “”, the empty string.

A string literal can be assigned to a string or an integral type. If their size differs the literal is right justified and either truncated on the left or zero filled on the left, as necessary.

e.g.

byte c = "A";                      // assign to c "A"

bit [10:0] a = "x41"; // assigns to a ‘b000_0100_0001

bit [1:4][7:0] h = "hello" ;    // assigns to h "ello"

String Functions

• len()  str.len() returns the length of the string, i.e., the number of characters in the string (excluding any terminating character).
• putc() str.putc(i, c) replaces the ith character in str with the given integral value.
• getc() str.getc(i) returns the ASCII code of the ith character in str.
• toupper() str.toupper() returns a string with characters in str converted to uppercase.
• tolower() str.tolower() returns a string with characters in str converted to lowercase.
• compare() str.compare(s) compares str and s, as in the ANSI C strcmp function (with regard to lexical ordering and return value), and embedded null bytes are included.
• icompare() str.icompare(s) compares str and s, like the ANSI C strcmp function (with regard to lexical ordering and return value), but the comparison is case insensitive and embedded null bytes are included.
• substr() str.substr(i, j) returns a new string that is a substring formed by characters in position i through j of str.
• atoi() str.atoi() returns the integer corresponding to the ASCII decimal representation in str. atohex(), atooct(), atobin() interprets the string as  hexadecimal, octal and binary values respectively.
• atoreal() str.atoreal() returns the real number corresponding to the ASCII decimal representation in str.
• itoa() str.itoa(i) stores the ASCII decimal representation of i into str (inverse of atoi).
• hextoa() str.hextoa(i) stores the ASCII hexadecimal representation of i into str (inverse of atohex).
• octtoa() str.octtoa(i) stores the ASCII octal representation of i into str (inverse of atooct).
• bintoa() str.bintoa(i) stores the ASCII binary representation of i into str (inverse of atobin).
• realtoa() str.realtoa(r) stores the ASCII real representation of i into str (inverse of atoreal).

Event Data Type

Unlike verilog, SystemVerilog events have a persistent triggered state that lasts for the duration of the entire time step. In verilog race condition may occure between event triggering and event sampling.In addition, an event variable can be assigned another event variable or the special value null. When assigned another event variable, both event variables refer to the same synchronization object. When assigned null, the association between the synchronization object and the event variable is broken. Events can be passed as arguments to tasks.

e.g.

module event_m;
event a,b;

initial
begin
#20 -> a;
b = a;
#20 -> a;
end

always @(a)
$display(" EVENT A is triggered ");

always @(b)
$display(" EVENT B is triggered ");

endmodule

User-defined Data Type

The user can define a new type using typedef, as in C.

typedef int intP;

This can then be instantiated as:

 intP a, b;  // a and b are of type int

Enumerated Data Type

An enumerated type declares a set of integral named constants. Enumerated data types provide the capability to abstractly declare strongly typed variables without either a data type or data value(s) and later add the required data type and value(s) for designs that require more definition.

In the absence of a data type declaration, the default data type shall be int. Any other data type used with enumerated types shall require an explicit data type declaration.

e.g.

module enums;
typedef enum {red, yellow, green} colour;
colour variable;

initial
begin
variable = red;
$display(" variable = %s ",variable.name() );
variable = yellow;
$display(" variable = %s ",variable.name() );
variable = green;
$display(" variable = %s ",variable.name() );
end
endmodule

Result:

variable = red
variable = yellow
variable = green

Enumerated Methods

• first() – The first method returns the value of the first member of the enumeration.
• last() – The last method returns the value of the last member of the enumeration.
• next() – The next() method returns the Nth next enumeration value (default is the next one) starting from the current value of the given variable.
• prev() – The prev() method returns the Nth previous enumeration value (default is the previous one) starting from the current value of the given variable.
• name() – The name() method returns the string representation of the given enumeration value. If the given value is not a member of the enumeration, the name() method returns the empty string.
  

Enumerated types in numerical expressions

Elements of enumerated type variables can be used innumerical expressions. The value used in the expression is the numerical value associated with the enumerated value.

e.g.

}IR;           // anonymous structure defines variable IR

IR.opcode = 1;           // set field in IR.

Packed Structures

A packed structure consists of bit fields, which are packed together in memory without gaps. This means that they are easily converted to and from bit vectors. The structures are declared using the packed keyword, which can be followed by the signed or unsigned keywords according to the desired arithmetic behavior. The default is unsigned.

struct packed signed {
int a;
shortint b;
byte c;
bit [7:0] d;
} pack1;            // signed, 2-state

Unpacked Structures

An unpacked structure has an implementation-dependent packing, normally matching the C compiler. The signing of unpacked structures is not allowed.

typedef struct {
bit [7:0] opcode;
bit [23:0] addr;
} instruction;      // named structure type
instruction IR;    // define variable

Packed Unions

A packed union shall contain members that must be packed structures, or packed arrays or integer data types all of the same size (in contrast to an unpacked union, where the members can be different sizes).

typedef union packed { // default unsigned
instruction acell;
bit [423:0] bit_slice;
bit [52:0][7:0] byte_slice;
} u_atmcell;

Unpacked Unions

Unlike structures, the components of a union all refer to the same location in memory. In this way, a union can be used at various times to hold different types of objects, without the need to create a separate object for each new type.

typedef union { // default unsigned
instruction acell;
bit [423:0] bit_slice;
bit [52:0][7:0] byte_slice;
} u_atmcell;

Classes

A class is a collection of data and a set of subroutines that operate on that data. The data in a class are referred to as class properties, and its subroutines are called methods. The class properties and methods, taken together, define the contents and capabilities of a class instance or object.

The object-oriented class extension allows objects to be created and destroyed dynamically. Class instances, or objects, can be passed around via object handles, which add a safe-pointer capability to the language. An object can be declared as an argument with direction input, output, inout, or ref. In each case, the argument copied is the object handle, not the contents of the object.

e.g.

class Packet;
int address;               // Properties are address, data, and crc
bit [63:0] data;
shortint crc;
Packet next;               // Handle to another Packet
function new();         // Methods are send and new
function bit send();
endclass : Packet